Time delay elements or shift registers are easily fabricated in integrated circuit technology. An input signal, delivered to the input terminal of a shift register, will not appear at the output terminal of the shift register until one cycle of the applicable clock has occurred. If one strings together a series of n such shift register modules, as illustrated in FIG. 1 where n=5, a signal, delivered to the input terminal of a first register D.sub.1 will appear n clock cycles later at the output terminal of register D.sub.n. Substantially all of the shift registers or delay lines built and offered for sale by various manufacturers have a fixed length or time delay, usually ranging from a time delay of as low as eight time units to as high as many thousands of time units.
A shift register or delay line that has a programmable length that varies over a sequence of times n.DELTA.t, wherein equals 1,2, . . . ,N, would be a useful component in the design of general purpose and special purpose computers. FIG. 2 illustrates one straightforward approach to provision of such a switch register. If switch SW1 is closed and all other switches are open, the output signal will be delayed one time unit .DELTA.t relative to the input signal. If switch SW5 is closed and all other switches are open, the output signal will be delayed by a time 5.DELTA.t relative to the input signal, for example.
This variable delay shift register is straightforward and easy to understand, but it carries with it certain problems. First, for a shift register of maximum length N, where N is a positive integer, N switches are needed to implement this shift register. This introduces a significant amount of additional circuitry and logic to select which switch is to be closed. Second, the output signal from each time delay element or shift register module must be routed to two places; to the input of the next time delay element, which is easy to do, and to the switch matrix, which may be much more difficult. This carries with it a chip area penalty and forces a substantial increase in cost for such a shift register vis-a-vis a standard, fixed length shift register. Third, the output terminal is connected to N switches. Although only one of these switches is in the "on" position, the remaining N-1 "off" switches represent a significant parasitic load that would limit the performance of such a shift register. One example of this approach is disclosed in U.S. Pat. No. 4,330,750, issued to Mayor for "Variable Delay Circuits."
FIG. 3 illustrates another approach to a variable length shift register from the prior art that allows time delays from .DELTA.t to 32.DELTA.t in integral multiples of the unit .DELTA.t. For example, with (only) switches SW1, SW2, SW3, SW4 and SW5 activated so that bypasses 1, 2 and 3 are not used but the remaining bypasses are used, the total delay would be .DELTA.t+2.DELTA.t+4.DELTA.t=7.DELTA.t. As another example, if switches SW2, SW3, SW6 and SW7 are activated so that bypasses number 2 and number 4 are not used, the corresponding time delay is 2.DELTA.t+8.DELTA.t=10.DELTA.t. All combinations of times from .DELTA.t to 32.DELTA.t may be implemented using the prior art device shown in FIG. 3. For a maximum time delay of M=2.sup.K time units .DELTA.t, (K=1,2,3, . . . ) precisely 2K switches are needed; K=5 in the example shown in FIG. 3. Where a combination of time delays up to 1024.DELTA.t= 2.sup.10 .DELTA.t, twenty switches would be required. The device shown in FIG. 3 offers a more compact implementation of a variable length shift register, using a reduced number of switches. A configuration incorporating the technique of FIG. 3 is disclosed in U.S. Pat. No. 4,016,511, issued to Ramsey and Post for a "Programmable Variable Length High Speed Digital Delay Line."
However, certain disadvantages are evident from the configuration illustrated in FIG. 3. First, the individual switches are more complex because, for example, switches SW2 and SW3 must work in unison. Second, implementation of the switches will cause each switch to have its own characteristic time delay, and the time delay (for passage through the switch itself) may be different for a switch in the activated or in the inactivated state. This will introduce variable incremental time delay (a fraction of .DELTA.t) on top of the variable time delay sought by use of the apparatus shown in FIG. 3. Third, if the length of the shift register is changed during operation of the device ("on the fly"), it is a matter of some complexity to determine the number of clock cycles required before the device has cleared itself for subsequent operation.
An interesting variation on this general approach is disclosed by U.S. Pat. No. 4,530,107, issued to Williams for a "Shift Register Delay Circuit," wherein one set of registers is used to determine coarse time delay (integral time units) and a second set of registers is used to determine fine time delay (fractions of a time unit).